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» Global delay optimization using structural choices
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VTS
1996
IEEE
112views Hardware» more  VTS 1996»
15 years 3 months ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker
PAMI
2008
147views more  PAMI 2008»
14 years 11 months ago
Image Stitching Using Structure Deformation
The aim of this paper is to achieve seamless image stitching without producing visual artifact caused by severe intensity discrepancy and structure misalignment, given that the inp...
Jiaya Jia, Chi-Keung Tang
ICDCS
1995
IEEE
15 years 3 months ago
A Competitive Analysis for Retransmission Timeout
Protocols that provide reliable communicationon top of a network that can lose packets rely on periodically retransmitting packets. The choice of retransmission timeout critically...
Shlomi Dolev, Michael Kate, Jennifer L. Welch
DAC
2009
ACM
16 years 22 days ago
Timing-driven optimization using lookahead logic circuits
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
Mihir R. Choudhury, Kartik Mohanram
MP
2002
84views more  MP 2002»
14 years 11 months ago
A decomposition procedure based on approximate Newton directions
The efficient solution of large-scale linear and nonlinear optimization problems may require exploiting any special structure in them in an efficient manner. We describe and analy...
Antonio J. Conejo, Francisco J. Nogales, Francisco...