591 search results - page 6 / 119 » Global delay optimization using structural choices |
119
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DAC
2006
ACM
16 years 18 days ago
2006
ACM
In this paper, we propose an exact algorithm for the problem of area optimization under a delay constraint in the synthesis of multiplierless FIR filters. To the best of our knowl...
134
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DAC
2000
ACM
16 years 18 days ago
2000
ACM
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
104
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ISPD
1997
ACM
15 years 3 months ago
1997
ACM
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
105
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ISLPED
2007
ACM
15 years 1 months ago
2007
ACM
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
ICCAD
2000
IEEE
15 years 4 months ago
2000
IEEE
This paper addresses the issue of timing driven gate duplication for delay optimization. Gate duplication has been used extensively for cutset minimization but the usefulness in m...