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» Global delay optimization using structural choices
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DAC
1999
ACM
15 years 7 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
EUROGP
2001
Springer
124views Optimization» more  EUROGP 2001»
15 years 7 months ago
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
An evolutionary algorithm is used to design a finite impulse response digital filter with reduced power consumption. The proposed design approach combines genetic optimization an...
Massimiliano Erba, Roberto Rossi, Valentino Libera...
ICCAD
2003
IEEE
134views Hardware» more  ICCAD 2003»
16 years 5 days ago
Multi-Domain Clock Skew Scheduling
The application of general clock skew scheduling is practically limited due to the difficulties in implementing a wide spectrum of dedicated clock delays in a reliable manner. Th...
Kaushik Ravindran, Andreas Kuehlmann, Ellen Sentov...
138
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MOBIHOC
2008
ACM
16 years 2 months ago
Delegation forwarding
Mobile opportunistic networks are characterized by unpredictable mobility, heterogeneity of contact rates and lack of global information. Successful delivery of messages at low co...
Vijay Erramilli, Mark Crovella, Augustin Chaintrea...
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
15 years 9 months ago
Multiple-Width Bus Partitioning Approach to Datapath Synthesis
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
Arash Ahmadi, Mark Zwolinski