Sciweavers

75 search results - page 6 / 15
» Good Architecture = Good (ADL Practices)
Sort
View
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
15 years 6 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
79
Voted
RE
2004
Springer
15 years 2 months ago
Architecture-driven Problem Decomposition
Jackson’s Problem Frames provide a means of analysing and decomposing problems. They emphasise the world outside the computer helping the developer to focus on the problem domai...
Lucia Rapanotti, Jon G. Hall, Michael Jackson, Bas...
81
Voted
APCSAC
2005
IEEE
15 years 3 months ago
Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
Shu Xiao, Edmund Ming-Kit Lai, A. Benjamin Premkum...
74
Voted
ISPW
2010
IEEE
15 years 1 months ago
Software Process Model Blueprints
Abstract. Explicitly defining a software process model is widely recognized as a good software engineering practice. However, having a defined process does not necessarily mean tha...
Julio Ariel Hurtado Alegria, Alejandro Lagos, Alex...
DEBS
2010
ACM
15 years 1 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...