127 search results - page 26 / 26 » Graph Based Representation of Dynamic Planning |
139
click to vote
FPGA
2010
ACM
16 years 8 days ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
171
Voted
WABI
2009
Springer
15 years 10 months ago
2009
Springer
Background: Frameshift mutations in protein-coding DNA sequences produce a drastic change in the resulting protein sequence, which prevents classic protein alignment methods from ...