5889 search results - page 103 / 1178 » Graph Layout Problems |
115
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ICCAD
2001
IEEE
15 years 11 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
83
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DAM
2010
15 years 2 months ago
2010
In this paper we investigate how graph problems that are NP-hard in general, but polynomially solvable on split graphs, behave on input graphs that are close to being split. For t...
106
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TVLSI
2010
14 years 9 months ago
2010
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
107
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ICFEM
2000
Springer
15 years 5 months ago
2000
Springer
A family of well known problems on graphs includingthe shortest path problem and the data flow analysis problem can be uniformly formulated as a fixed-point problem on graphs. We ...
114
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CORR
2008
Springer
15 years 2 months ago
2008
Springer
In this paper we present an algorithmic framework for solving a class of combinatorial optimization problems on graphs with bounded pathwidth. The problems are NP-hard in general, ...