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141
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CASES
2008
ACM
15 years 5 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
125
Voted
ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
15 years 9 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
120
Voted
ICWS
2004
IEEE
15 years 5 months ago
Dynamic Data Integration Using Web Services
We address the problem of large-scale data integration, where the data sources are unknown at design time, are from autonomous organisations, and may evolve. Experiments are descr...
Fujun Zhu, Mark Turner, Ioannis A. Kotsiopoulos, K...
128
Voted
RTSS
1998
IEEE
15 years 8 months ago
Real-Time Scheduling in a Generic Fault-Tolerant Architecture
Previous ultra-dependable real-time computing architectures have been specialised to meet the requirements of a particular application domain. Over the last two years, a consortiu...
Andy J. Wellings, Ljerka Beus-Dukic, David Powell
142
Voted
EMSOFT
2008
Springer
15 years 5 months ago
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models
Aimed at verifying safety properties and improving simulation coverage for hybrid systems models of embedded control software, we propose a technique that combines numerical simul...
Rajeev Alur, Aditya Kanade, S. Ramesh, K. C. Shash...