We study the model checking problem of timed automata based on SAT solving. Our work investigates alternative possibilities for coding the SAT reductions that are based on parallel...
Abstract—Many applications are concurrent and communicate over a network. The non-determinism in the thread and communication schedules makes it desirable to model check such sys...
A new courtesy amount recognition module of CENPARMI’s Check Reading System (CRS) is proposed in this paper. The module consists of 3 main segments: pre-processing, segmentation...
We present a component-based description language for heterogeneous systems composed of several data flow processing components and a unique eventbased controller. Descriptions a...
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...