3335 search results - page 108 / 667 » Grid result checking |
150
Voted
CADE
2012
Springer
13 years 5 months ago
2012
Springer
We propose a word level, bounded model checking (BMC) algorithm based on translation into the effectively propositional fragment (EPR) of firstorder logic. This approach to BMC al...
111
Voted
FMCAD
2008
Springer
15 years 5 months ago
2008
Springer
The quality of formal specifications and the circuits they are written for can be evaluated through checks such as vacuity and coverage. Both checks involve mutations to the specif...
124
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ICCAD
2006
IEEE
16 years 9 days ago
2006
IEEE
The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulat...
111
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ICCAD
2005
IEEE
16 years 8 days ago
2005
IEEE
Abstract— In bounded model checking (BMC)-based verification flows lack of reachability constraints often leads to false negatives. At present, it is daily practice of a veri...
130
Voted
DSD
2009
IEEE
15 years 10 months ago
2009
IEEE
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...