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125
Voted
DATE
1999
IEEE
135views Hardware» more  DATE 1999»
15 years 7 months ago
Combinational Equivalence Checking Using Satisfiability and Recursive Learning
The problem of checking the equivalence of combinational circuits is of key significance in the verification of digital circuits. In recent years, several approaches have been pro...
João P. Marques Silva, Thomas Glass
142
Voted
DATE
2004
IEEE
97views Hardware» more  DATE 2004»
15 years 7 months ago
A Formal Verification Methodology for Checking Data Integrity
Formal verification techniques have been playing an important role in pre-silicon validation processes. One of the most important points considered in performing formal verificati...
Yasushi Umezawa, Takeshi Shimizu
CMSB
2006
Springer
15 years 7 months ago
Probabilistic Model Checking of Complex Biological Pathways
Abstract. Probabilistic model checking is a formal verification technique that has been successfully applied to the analysis of systems from a broad range of domains, including sec...
John Heath, Marta Z. Kwiatkowska, Gethin Norman, D...
132
Voted
FM
2006
Springer
146views Formal Methods» more  FM 2006»
15 years 7 months ago
Exact and Approximate Strategies for Symmetry Reduction in Model Checking
Symmetry reduction techniques can help to combat the state space explosion problem for model checking, but are restricted by the hard problem of determining equivalence of states d...
Alastair F. Donaldson, Alice Miller
151
Voted
SPIN
2000
Springer
15 years 7 months ago
Model Checking Based on Simultaneous Reachability Analysis
Abstract. Simultaneous reachability analysis SRA is a recently proposed approach to alleviating the state space explosion problem in reachability analysis of concurrent systems. Th...
Bengi Karaçali, Kuo-Chung Tai