3335 search results - page 134 / 667 » Grid result checking |
140
click to vote
CAV
2012
Springer
13 years 6 months ago
2012
Springer
A SAT-based incremental, inductive algorithm for model checking CTL properties is proposed. As in classic CTL model checking, the parse graph of the property shapes the analysis. H...
227
Voted
ECOOP
2009
Springer
16 years 4 months ago
2009
Springer
Reusable APIs often dene usage protocols. We previously developed a sound modular type system that checks compliance with typestate-based protocols while aording a great deal of al...
132
Voted
ISMVL
2009
IEEE
15 years 10 months ago
2009
IEEE
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits’ primary inputs and outputs must be in pure logic states ...
138
click to vote
IFM
2009
Springer
15 years 10 months ago
2009
Springer
We present the new technique of dynamic path reduction (DPR), which allows one to prune redundant paths from the state space of a program under verification. DPR is a very general...
94
Voted
DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...