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ASPLOS
2006
ACM
15 years 7 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
MM
2006
ACM
218views Multimedia» more  MM 2006»
15 years 7 months ago
SmartLabel: an object labeling tool using iterated harmonic energy minimization
Labeling objects in images is an essential prerequisite for many visual learning and recognition applications that depend on training data, such as image retrieval, object detecti...
Wen Wu, Jie Yang
101
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SIGMETRICS
2006
ACM
15 years 7 months ago
Robust network connectivity: when it's the big picture that matters
This work analyzes the connectivity of large diameter networks where every link has an independent probability p of failure. We give a (relatively simple) topological condition th...
Enoch Peserico, Larry Rudolph
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Optimal module and voltage assignment for low-power
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
Deming Chen, Jason Cong, Junjuan Xu
ER
2005
Springer
200views Database» more  ER 2005»
15 years 7 months ago
How to Tame a Very Large ER Diagram (Using Link Analysis and Force-Directed Drawing Algorithms)
Abstract. Understanding a large schema without the assistance of persons already familiar with it (and its associated applications), is a hard and very time consuming task that occ...
Yannis Tzitzikas, Jean-Luc Hainaut