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TC
2008
15 years 4 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
SOSE
2008
IEEE
15 years 10 months ago
Towards SOA-Based Code Defect Analysis
Static code analysis is the analysis of software that is performed to acquire information concerning the dynamic behavior of programs built from that software, without actually ex...
Qianxiang Wang, Na Meng, Zhiyi Zhou, Jinhui Li, Ho...
144
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KBSE
1997
IEEE
15 years 8 months ago
Modular Flow Analysis for Concurrent Software
Modern software systems are designed and implemented in a modular fashion by composing individual components. Early validation of individual module designs and implementations off...
Matthew B. Dwyer
CSUR
1999
114views more  CSUR 1999»
15 years 3 months ago
Directions for Research in Approximate System Analysis
useful for optimizing compilers [15], partial evaluators [11], abstract debuggers [1], models-checkers [2], formal verifiers [13], etc. The difficulty of the task comes from the fa...
Patrick Cousot
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
15 years 10 months ago
Use of statistical timing analysis on real designs
A vast literature has been published on Statistical Static Timing Analysis (SSTA), its motivations, its different implementations and their runtime/accuracy trade-offs. However, v...
A. Nardi, Emre Tuncer, S. Naidu, A. Antonau, S. Gr...