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VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 2 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
PE
2002
Springer
132views Optimization» more  PE 2002»
15 years 1 months ago
Performance evaluation with temporal rewards
Today many formalisms exist for specifying complex Markov chains. In contrast, formalisms for specifying rewards, enabling the analysis of long-run average performance properties,...
Jeroen Voeten
SPIN
2000
Springer
15 years 5 months ago
The Temporal Rover and the ATG Rover
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
Doron Drusinsky
KDD
2007
ACM
177views Data Mining» more  KDD 2007»
16 years 2 months ago
Mining optimal decision trees from itemset lattices
We present DL8, an exact algorithm for finding a decision tree that optimizes a ranking function under size, depth, accuracy and leaf constraints. Because the discovery of optimal...
Élisa Fromont, Siegfried Nijssen
ICTAI
1992
IEEE
15 years 6 months ago
Automated Parameter Tuning in Stereo Vision Under Time Constraints
This paper presents a method for tuning parameters under a fixed time constraint for a general binocular stereo-vision algorithm. A major difficulty in stereo vision, as well as i...
Steven R. Schwartz, Benjamin W. Wah