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PVM
2004
Springer
15 years 3 months ago
A Refinement Strategy for a User-Oriented Performance Analysis
We introduce a refinement strategy to bring the parallel performance analysis closer to the user. The analysis starts with a simple high-level performance model. It is based on fir...
Jan Lemeire, Andy Crijns, John Crijns, Erik F. Dir...
ASAP
2003
IEEE
108views Hardware» more  ASAP 2003»
15 years 3 months ago
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
Terry Tao Ye, Giovanni De Micheli
92
Voted
EDOC
2003
IEEE
15 years 3 months ago
Integrating CBSE, SoC, MDA, and AOP in a Software Development Method
Component-Based Software Engineering, Separation of Concerns, Model-Driven Architecture, and Aspect-Oriented Programming are four active research areas that have been around for s...
Raul Silaghi, Alfred Strohmeier
ISADS
2003
IEEE
15 years 3 months ago
The Central Guardian Approach to Enforce Fault Isolation in the Time-Triggered Architecture
This paper discusses measures to make a distributed system based on the Time-Triggered Architecture resistant to arbitrary node failures. To achieve this, the presented approach i...
Günther Bauer, Hermann Kopetz, Wilfried Stein...
EUROPAR
2003
Springer
15 years 3 months ago
Exploiting On-Chip Data Transfers for Improving Performance of Chip-Scale Multiprocessors
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power efficient, and easier to test and validate. In this work, we focus on a...
Guangyu Chen, Mahmut T. Kandemir, Alok N. Choudhar...