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» Hardness Results and Efficient Algorithms for Graph Powers
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ATS
2004
IEEE
87views Hardware» more  ATS 2004»
15 years 1 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
15 years 6 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
HPCC
2007
Springer
15 years 4 months ago
Parallel Genetic Algorithms for DVS Scheduling of Distributed Embedded Systems
Many of today’s embedded systems, such as wireless and portable devices rely heavily on the limited power supply. Therefore, energy efficiency becomes one of the major design con...
Man Lin, Chen Ding
SIGMETRICS
2010
ACM
147views Hardware» more  SIGMETRICS 2010»
14 years 8 months ago
On random walks in direction-aware network problems
Graph theory provides a powerful set of metrics and conceptual ideas to model and investigate the behavior of communication networks. Most graph-theoretical frameworks in the netw...
Ali Tizghadam, Alberto Leon-Garcia
CPM
2007
Springer
134views Combinatorics» more  CPM 2007»
15 years 1 months ago
Efficient Computation of Substring Equivalence Classes with Suffix Arrays
This paper considers enumeration of substring equivalence classes introduced by Blumer et al. [1]. They used the equivalence classes to define an index structure called compact dir...
Kazuyuki Narisawa, Shunsuke Inenaga, Hideo Bannai,...