550 search results - page 35 / 110 » Hardware Accelerated Power Estimation |
116
Voted
ISCAS
2007
IEEE
15 years 10 months ago
2007
IEEE
—Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, we propose a heterogeneous p...
131
Voted
ISQED
2006
IEEE
15 years 9 months ago
2006
IEEE
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
136
Voted
ISPASS
2010
IEEE
15 years 10 months ago
2010
IEEE
—While many-core accelerator architectures, such as today’s Graphics Processing Units (GPUs), offer orders of magnitude more raw computing power than contemporary CPUs, their m...
141
Voted
ISPASS
2007
IEEE
15 years 10 months ago
2007
IEEE
The ongoing trend of increasing computer hardware and software complexity has resulted in the increase in complexity and overheads of cycle-accurate processor system simulation, e...
134
Voted
ISCAS
1999
IEEE
15 years 8 months ago
1999
IEEE
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...