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» Hardware Accelerated Power Estimation
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124
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CASES
2006
ACM
15 years 7 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...
143
Voted
ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 9 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
133
Voted
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
15 years 5 months ago
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is...
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Bab...
166
Voted
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
15 years 7 months ago
Predictive models for multimedia applications power consumption based on use-case and OS level analysis
—Power management at any abstraction level is a key issue for many mobile multimedia and embedded applications. In this paper a design workflow to generate system-level power mo...
Patrick Bellasi, William Fornaciari, David Siorpae...
121
Voted
VTC
2008
IEEE
15 years 10 months ago
A Bit-Mapping Strategy for Joint Iterative Channel Estimation and Turbo-Decoding
Abstract— In this paper, we investigate Turbo-coded transmission over a temporally correlated flat Rayleigh fading channel. Conventionally, channel estimation is performed prior...
Susanne Godtmann, Helge Lüders, Gerd Ascheid,...