Sciweavers

550 search results - page 46 / 110
» Hardware Accelerated Power Estimation
Sort
View
ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
15 years 8 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
16 years 16 days ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
199
Voted
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
14 years 3 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
138
Voted
FPGA
2010
ACM
197views FPGA» more  FPGA 2010»
15 years 7 months ago
A 3d-audio reconfigurable processor
Various multimedia communication systems based on 3DAudio algorithms have been proposed by researchers from the acoustic data processing domain. However, all systems reported in t...
Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi G...
110
Voted
ASPDAC
2004
ACM
107views Hardware» more  ASPDAC 2004»
15 years 9 months ago
Interconnect capacitance estimation for FPGAs
Abstract—The dynamic power consumed by a digital CMOS circuit is directly proportional to capacitance. In this paper, we consider pre-routing capacitance estimation for FPGAs and...
Jason Helge Anderson, Farid N. Najm