Sciweavers

550 search results - page 53 / 110
» Hardware Accelerated Power Estimation
Sort
View
157
Voted
FPL
2008
Springer
207views Hardware» more  FPL 2008»
15 years 5 months ago
Bitstream compression techniques for Virtex 4 FPGAs
This paper examines the opportunity of using compression for accelerating the (re)configuration of FPGA devices, focusing on the choice of compression algorithms, and their hardwa...
Radu Stefan, Sorin Dan Cotofana
DATE
2008
IEEE
149views Hardware» more  DATE 2008»
15 years 10 months ago
OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks
Accurate power and performance figures are critical to assess the effective design of possible sensor node architectures in Body Area Networks (BANs) since they operate on limite...
Francisco J. Rincón, Michele Paselli, Joaqu...
98
Voted
DAC
2008
ACM
16 years 4 months ago
Low power passive equalizer optimization using tritonic step response
A low power passive equalizer using RL terminator is proposed and optimized in this work. The equalizer includes an inductor in series with the resistive terminator, which boosts ...
Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch,...
119
Voted
DAC
2010
ACM
15 years 3 months ago
Performance and power modeling in a multi-programmed multi-core environment
This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-cor...
Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley M...
115
Voted
ICCAD
2003
IEEE
144views Hardware» more  ICCAD 2003»
16 years 14 days ago
A High-level Interconnect Power Model for Design Space Exploration
— In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications bet...
Pallav Gupta, Lin Zhong, Niraj K. Jha