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» Hardware Accelerated Power Estimation
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117
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ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
15 years 8 months ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh
151
Voted
DAC
2006
ACM
16 years 4 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
139
Voted
ICCD
2005
IEEE
176views Hardware» more  ICCD 2005»
16 years 14 days ago
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
Recent advances in Dynamic Power Management (DPM) techniques have resulted in designs that support a rich set of power management options, both at the hardware and software levels...
Shrirang M. Yardi, Karthik Channakeshava, Michael ...
PPAM
2007
Springer
15 years 9 months ago
A Grid-Enabled Lattice-Boltzmann-Based Modelling System
Lattice-Boltzmann (LB) methods are a well-known technique in the context of computational fluid dynamics. By nature, they can easily be parallelized but their adaptation to the Gr...
Gérard Dethier, Cyril Briquet, Pierre March...
135
Voted
ACCV
2006
Springer
15 years 9 months ago
Boosted Algorithms for Visual Object Detection on Graphics Processing Units
Nowadays, the use of machine learning methods for visual object detection has become widespread. Those methods are robust. They require an important processing power and a high mem...
Hicham Ghorayeb, Bruno Steux, Claude Laurgeau