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ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
16 years 12 days ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
135
Voted
DATE
2008
IEEE
76views Hardware» more  DATE 2008»
15 years 10 months ago
Signal Probability Based Statistical Timing Analysis
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...
Bao Liu
125
Voted
IPPS
2006
IEEE
15 years 9 months ago
Reconfigurable communications for image processing applications
: This work tries to reuse programmable communication resources like a Network-on-Chip (NoC) in the acceleration of image applications. We show a mathematical model for the computa...
André Borin Soares, Luigi Carro, Altamiro A...
122
Voted
ISLPED
2004
ACM
102views Hardware» more  ISLPED 2004»
15 years 9 months ago
Microarchitectural power modeling techniques for deep sub-micron microprocessors
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
Nam Sung Kim, Taeho Kgil, Valeria Bertacco, Todd M...
124
Voted
DATE
2006
IEEE
132views Hardware» more  DATE 2006»
15 years 9 months ago
Energy reduction by workload adaptation in a multi-process environment
Reducing energy consumption is an important issue in modern computers. Dynamic power management (DPM) has been extensively studied in recent years. One approach for DPM is to adju...
Changjiu Xian, Yung-Hsiang Lu