Sciweavers

550 search results - page 96 / 110
» Hardware Accelerated Power Estimation
Sort
View
ICCAD
2007
IEEE
103views Hardware» more  ICCAD 2007»
15 years 8 months ago
Enhancing design robustness with reliability-aware resynthesis and logic simulation
While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this...
Smita Krishnaswamy, Stephen Plaza, Igor L. Markov,...
ICCAD
2002
IEEE
103views Hardware» more  ICCAD 2002»
15 years 8 months ago
Synthesis of customized loop caches for core-based embedded systems
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
Susan Cotterell, Frank Vahid
ISLPED
2009
ACM
100views Hardware» more  ISLPED 2009»
15 years 6 months ago
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Post-fabrication tuning for mitigating manufacturing variability is receiving a significant attention. To reduce leakage increase involved in performance compensation by body bia...
Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuya...
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
15 years 4 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
14 years 3 months ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...