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» Hardware Acceleration of HMMER on FPGAs
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ARC
2010
Springer
387views Hardware» more  ARC 2010»
15 years 6 months ago
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
David Boland, George A. Constantinides
ISPAN
2005
IEEE
15 years 5 months ago
An FPGA-Based Floating-Point Jacobi Iterative Solver
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
Gerald R. Morris, Viktor K. Prasanna
FPL
2007
Springer
150views Hardware» more  FPL 2007»
15 years 3 months ago
Discrete Event Simulation of Molecular Dynamics with Configurable Logic
: Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretized ...
Josh Model, Martin C. Herbordt
FPL
2007
Springer
97views Hardware» more  FPL 2007»
15 years 3 months ago
An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee
ASPDAC
2001
ACM
120views Hardware» more  ASPDAC 2001»
15 years 3 months ago
Virtual Java/FPGA interface for networked reconfiguration
Abstract- Avirtual interfacebetweenJava andFPGA for networked reconfigurationis presented. ThroughtheJavaflFPGAinterface,Java applicationscan exploithardwareaccelerators with FPGAs...
Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, S...