Sciweavers

365 search results - page 19 / 73
» Hardware Architecture of a Parallel Pattern Matching Engine
Sort
View
IISWC
2008
IEEE
15 years 4 months ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
MAM
2006
125views more  MAM 2006»
14 years 9 months ago
Stream computations organized for reconfigurable execution
Reconfigurable systems can offer the high spatial parallelism and fine-grained, bit-level resource control traditionally associated with hardware implementations, along with the f...
André DeHon, Yury Markovsky, Eylon Caspi, M...
ISORC
2006
IEEE
15 years 3 months ago
Design Patterns for Releasing Applications in C++ Implementations of JTRS Software Communications Architecture
The Software Communications Architecture (SCA), which has been adopted as an SDR (Software Defined Radio) Forum standard, provides a framework that successfully exploits common de...
Michael Barth, Jonghun Yoo, Saehwa Kim, Seongsoo H...
DAC
2007
ACM
15 years 10 months ago
Hardware Support for Secure Processing in Embedded Systems
The inherent limitations of embedded systems make them particularly vulnerable to attacks. We have developed a hardware monitor that operates in parallel to the embedded processor...
Shufu Mao, Tilman Wolf
CSMR
1998
IEEE
15 years 1 months ago
Assessing Architectural Complexity
While it is widely agreed that architectural simplicity is a key factor to the success of large software systems, it is not obvious how to measure architectural complexity. Our ap...
Rick Kazman, M. Burth