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» Hardware Architecture of a Parallel Pattern Matching Engine
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CODES
2003
IEEE
15 years 2 months ago
A fast parallel reed-solomon decoder on a reconfigurable architecture
This paper presents a software implementation of a very fast parallel Reed-Solomon decoder on the second generation of MorphoSys reconfigurable computation platform, which is targ...
Arezou Koohi, Nader Bagherzadeh, Chengzi Pan
COMPSAC
2008
IEEE
15 years 4 months ago
Embedded Architecture Description Language
In the state-of-the-art hardware/software (HW/SW) codesign of embedded systems, there is a lack of sufficient support for architectural specifications across HW/SW boundaries. S...
Juncao Li, Nicholas T. Pilkington, Fei Xie, Qiang ...
INFSOF
2007
83views more  INFSOF 2007»
14 years 9 months ago
On the design of more secure software-intensive systems by use of attack patterns
Retrofitting security implementations to a released software-intensive system or to a system under development may require significant architectural or coding changes. These late...
Michael Gegick, Laurie Williams
ADAEUROPE
2010
Springer
15 years 2 months ago
AdaStreams: A Type-Based Programming Extension for Stream-Parallelism with Ada 2005
Because multicore CPUs have become the standard with all major hardware manufacturers, it becomes increasingly important for ing languages to provide programming abstractions that ...
Gingun Hong, Kirak Hong, Bernd Burgstaller, Johann...
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DAC
2008
ACM
15 years 10 months ago
Parallelizing CAD: a timely research agenda for EDA
The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on paralle...
Bryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su