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» Hardware Architecture of a Parallel Pattern Matching Engine
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ICS
2009
Tsinghua U.
15 years 4 months ago
Fast and scalable list ranking on the GPU
General purpose programming on the graphics processing units (GPGPU) has received a lot of attention in the parallel computing community as it promises to offer the highest perfo...
M. Suhail Rehman, Kishore Kothapalli, P. J. Naraya...
CGO
2007
IEEE
15 years 4 months ago
Loop Optimization using Hierarchical Compilation and Kernel Decomposition
The increasing complexity of hardware features for recent processors makes high performance code generation very challenging. In particular, several optimization targets have to b...
Denis Barthou, Sébastien Donadio, Patrick C...
DAC
2002
ACM
15 years 10 months ago
A flexible accelerator for layer 7 networking applications
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
Gokhan Memik, William H. Mangione-Smith
CODES
2003
IEEE
15 years 2 months ago
Deriving process networks from weakly dynamic applications in system-level design
We present an approach to the automatic derivation of executable Process Network specifications from Weakly Dynamic Applications. We introduce the notions of Dynamic Single Assig...
Todor Stefanov, Ed F. Deprettere
ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
15 years 1 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...