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» Hardware Architecture of a Parallel Pattern Matching Engine
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DEBS
2007
ACM
15 years 1 months ago
Architect's dream or developer's nightmare?
Architectural principles such as loose coupling are the key drivers behind the adoption of service-oriented architectures. Service-oriented architectures promote concepts such as c...
Gregor Hohpe
96
Voted
ICPP
2008
IEEE
15 years 4 months ago
VELO: A Novel Communication Engine for Ultra-Low Latency Message Transfers
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...
Heiner Litz, Holger Fröning, Mondrian Nü...
PDIS
1991
IEEE
15 years 1 months ago
Practical Prefetching Techniques for Parallel File Systems
Improvements in the processing speed of multiprocessors are outpacing improvements in the speed of disk hardware. Parallel disk I/O subsystems have been proposed as one way to clo...
David Kotz, Carla Schlatter Ellis
101
Voted
APAQS
2001
IEEE
15 years 1 months ago
Object-Oriented Program Behavior Analysis Based on Control Patterns
Code-patterns are statically recurring structure specific to a programming language. It can be parallel to aid in designing software systems for solving particular problems. Contr...
C.-C. Hwang, S.-K. Huang, D.-J. Chen, D. Chen
ASAP
2008
IEEE
161views Hardware» more  ASAP 2008»
14 years 11 months ago
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posterio...
Yang Sun, Yuming Zhu, Manish Goel, Joseph R. Caval...