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» Hardware Architecture of a Parallel Pattern Matching Engine
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DSD
2002
IEEE
110views Hardware» more  DSD 2002»
15 years 2 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...
HIPEAC
2010
Springer
15 years 1 months ago
Accelerating XML Query Matching through Custom Stack Generation on FPGAs
Abstract. Publish-subscribe systems present the state of the art in information dissemination to multiple users. Such systems have evolved from simple topic-based to the current XM...
Roger Moussalli, Mariam Salloum, Walid A. Najjar, ...
VLSISP
2008
132views more  VLSISP 2008»
14 years 9 months ago
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames f...
Brian M. H. Li, Philip Heng Wai Leong
ANCS
2007
ACM
15 years 1 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos
GVD
2009
191views Database» more  GVD 2009»
14 years 7 months ago
Query Processing on Multi-Core Architectures
The upcoming generation of computer hardware poses several new challenges for database developers and engineers. Software in general and database management systems (DBMSs) in par...
Frank Huber, Johann Christoph Freytag