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» Hardware Architecture of a Parallel Pattern Matching Engine
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IPPS
2008
IEEE
15 years 4 months ago
Design of steering vectors for dynamically reconfigurable architectures
An architectural framework is studied that can perform dynamic reconfiguration. A basic objective is to dynamically reconfigure the architecture so that its configuration is well ...
Nick A. Mould, Brian F. Veale, John K. Antonio, Mo...
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 1 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
ISPASS
2009
IEEE
15 years 4 months ago
Evaluating GPUs for network packet signature matching
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such servi...
Randy Smith, Neelam Goyal, Justin Ormont, Karthike...
ISCA
2008
IEEE
105views Hardware» more  ISCA 2008»
15 years 4 months ago
Intra-disk Parallelism: An Idea Whose Time Has Come
Server storage systems use a large number of disks to achieve high performance, thereby consuming a significant amount of power. In this paper, we propose to significantly reduc...
Sriram Sankar, Sudhanva Gurumurthi, Mircea R. Stan
ASPLOS
2010
ACM
15 years 4 months ago
MacroSS: macro-SIMDization of streaming applications
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Ku...