Sciweavers

365 search results - page 33 / 73
» Hardware Architecture of a Parallel Pattern Matching Engine
Sort
View
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
15 years 4 months ago
Architectural leakage-aware management of partitioned scratchpad memories
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be ev...
Olga Golubeva, Mirko Loghi, Massimo Poncino, Enric...
CASES
2007
ACM
15 years 1 months ago
Compiler generation from structural architecture descriptions
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
Florian Brandner, Dietmar Ebner, Andreas Krall
IPPS
2003
IEEE
15 years 2 months ago
Approximate Search Engine Optimization for Directory Service
Today, in many practical E-Commerce systems, the real stored data usually are short strings, such as names, addresses, or other information. Searching data within these short stri...
Kai-Hsiang Yang, Chi-Chien Pan, Tzao-Lin Lee
SBACPAD
2003
IEEE
180views Hardware» more  SBACPAD 2003»
15 years 2 months ago
New Parallel Algorithms for Frequent Itemset Mining in Very Large Databases
Frequent itemset mining is a classic problem in data mining. It is a non-supervised process which concerns in finding frequent patterns (or itemsets) hidden in large volumes of d...
Adriano Veloso, Wagner Meira Jr., Srinivasan Parth...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 3 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...