365 search results - page 35 / 73 » Hardware Architecture of a Parallel Pattern Matching Engine |
78
Voted
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
ISCAS
2005
IEEE
15 years 3 months ago
2005
IEEE
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
88
Voted
WCRE
2003
IEEE
15 years 2 months ago
2003
IEEE
Our research goal is to retarget image processing programs written in sequential languages (e.g., C) to architectures with data-parallel processing capabilities. Image processing ...
WCET
2010
14 years 7 months ago
2010
To meet performance requirements as well as constraints on cost and power consumption, future embedded systems will be designed with multi-core processors. However, the question o...
GECCO
2007
Springer
15 years 3 months ago
2007
Springer
Engineering design increasingly uses computer simulation models coupled with optimization algorithms to find the best design that meets the customer constraints within a time con...