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» Hardware Architecture of a Parallel Pattern Matching Engine
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ARC
2006
Springer
124views Hardware» more  ARC 2006»
15 years 1 months ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
ISPEC
2005
Springer
15 years 3 months ago
An Email Worm Vaccine Architecture
We present an architecture for detecting “zero-day” worms and viruses in incoming email. Our main idea is to intercept every incoming message, prescan it for potentially danger...
Stelios Sidiroglou, John Ioannidis, Angelos D. Ker...
IEEEPACT
2006
IEEE
15 years 3 months ago
Two-level mapping based cache index selection for packet forwarding engines
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
Kaushik Rajan, Ramaswamy Govindarajan
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
15 years 4 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
PC
2007
343views Management» more  PC 2007»
14 years 9 months ago
Runtime scheduling of dynamic parallelism on accelerator-based multi-core systems
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
Filip Blagojevic, Dimitrios S. Nikolopoulos, Alexa...