365 search results - page 41 / 73 » Hardware Architecture of a Parallel Pattern Matching Engine |
92
Voted
VLSID
2001
IEEE
15 years 10 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
129
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WOSP
1998
ACM
15 years 1 months ago
1998
ACM
The POEMS project is creating an environment for end-to-end performance modeling of complex parallel and distributed systems, spanning the domains of application software, runti...
IEEEPACT
2007
IEEE
15 years 4 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ARCS
2006
Springer
15 years 1 months ago
2006
Springer
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...