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» Hardware Architecture of a Parallel Pattern Matching Engine
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ISORC
2005
IEEE
15 years 3 months ago
Self-Tuning Planned Actions Time to Make Real-Time SOAP Real
This paper proposes a new method for programming and controlling distributed tasks. Applications declare behavior patterns that are used to automatically predict and reserve resou...
Johannes Helander, Stefan B. Sigurdsson
IEEEPACT
2006
IEEE
15 years 3 months ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...
CGO
2006
IEEE
15 years 3 months ago
Compiling for EDGE Architectures
Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
Aaron Smith, Jon Gibson, Bertrand A. Maher, Nichol...
IWPC
2006
IEEE
15 years 3 months ago
Alborz: An Interactive Toolkit to Extract Static and Dynamic Views of a Software System
: Alborz is a multi-view, interactive, and wizard-based software architecture reconstruction and evaluation toolkit that takes advantage of the Eclipse plug-in technology to provid...
Kamran Sartipi, Lingdong Ye, Hossein Safyallah
CLUSTER
2000
IEEE
15 years 2 months ago
Design and Performance of Maestro Cluster Network
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada