365 search results - page 50 / 73 » Hardware Architecture of a Parallel Pattern Matching Engine |
ISCA
2008
IEEE
15 years 4 months ago
2008
IEEE
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
101
Voted
EUROPAR
1999
Springer
15 years 1 months ago
1999
Springer
Two-level predictors deliver highly accurate conditional branch prediction, indirect branch target prediction and value prediction. Accurate prediction enables speculative executio...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...
102
Voted
HPCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
WWW
2009
ACM
15 years 10 months ago
2009
ACM
Web search engines are facing formidable performance challenges as they need to process thousands of queries per second over billions of documents. To deal with this heavy workloa...