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» Hardware Architecture of a Parallel Pattern Matching Engine
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SIGMETRICS
2010
ACM
213views Hardware» more  SIGMETRICS 2010»
15 years 2 months ago
Small subset queries and bloom filters using ternary associative memories, with applications
Associative memories offer high levels of parallelism in matching a query against stored entries. We design and analyze an architecture which uses a single lookup into a Ternary C...
Ashish Goel, Pankaj Gupta
TVLSI
2002
111views more  TVLSI 2002»
14 years 9 months ago
Circular BIST with state skipping
Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simp...
Nur A. Touba
SEMWEB
2010
Springer
14 years 7 months ago
Optimizing Enterprise-Scale OWL 2 RL Reasoning in a Relational Database System
OWL 2 RL was standardized as a less expressive but scalable subset of OWL 2 that allows a forward-chaining implementation. However, building an enterprise-scale forward-chaining ba...
Vladimir Kolovski, Zhe Wu, George Eadon
SPAA
1995
ACM
15 years 1 months ago
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent yea...
Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias,...
PVLDB
2010
166views more  PVLDB 2010»
14 years 8 months ago
Complex Event Detection at Wire Speed with FPGAs
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many complex event pr...
Louis Woods, Jens Teubner, Gustavo Alonso