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» Hardware Architecture of a Parallel Pattern Matching Engine
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IJCNN
2007
IEEE
15 years 3 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...
SOSP
1997
ACM
14 years 11 months ago
Towards Transparent and Efficient Software Distributed Shared Memory
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...
Daniel J. Scales, Kourosh Gharachorloo
ICCAD
2006
IEEE
180views Hardware» more  ICCAD 2006»
15 years 6 months ago
A bitmask-based code compression technique for embedded systems
Embedded systems are constrained by the available memory. Code compression techniques address this issue by reducing the code size of application programs. Dictionary-based code c...
Seok-Won Seong, Prabhat Mishra
MICRO
1997
IEEE
116views Hardware» more  MICRO 1997»
15 years 1 months ago
Tuning Compiler Optimizations for Simultaneous Multithreading
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay ...
CGF
2008
217views more  CGF 2008»
14 years 9 months ago
A Flexible Kernel for Adaptive Mesh Refinement on GPU
We present a flexible GPU kernel for adaptive on-the-fly refinement of meshes with arbitrary topology. By simply reserving a small amount of GPU memory to store a set of adaptive ...
Tamy Boubekeur, Christophe Schlick