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» Hardware Architecture of a Parallel Pattern Matching Engine
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ESANN
2008
14 years 11 months ago
Neural network hardware architecture for pattern recognition in the HESS2 project
In this paper, we consider the problem of implementation of neural network in the context of the level 2 trigger of HESS2 project. We propose a hardware architecture which which ta...
Narayanan Ramanan, Sonia Khatchadourian, Jean-Chri...
EUC
2007
Springer
15 years 1 months ago
Parallel Network Intrusion Detection on Reconfigurable Platforms
With the wide adoption of internet into our everyday lives, internet security becomes an important issue. Intrusion detection at the network level is an effective way of stopping m...
Chun Xue, Zili Shao, Meilin Liu, Qingfeng Zhuge, E...
ASPDAC
2006
ACM
173views Hardware» more  ASPDAC 2006»
15 years 1 months ago
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking
A novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching, as well as its FPGA/ASIC implementation architecture are presented. With ...
K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tet...
CCS
2011
ACM
13 years 9 months ago
MIDeA: a multi-parallel intrusion detection architecture
Network intrusion detection systems are faced with the challenge of identifying diverse attacks, in extremely high speed networks. For this reason, they must operate at multi-Giga...
Giorgos Vasiliadis, Michalis Polychronakis, Sotiri...
TREC
2001
14 years 11 months ago
SiteQ: Engineering High Performance QA System Using Lexico-Semantic Pattern Matching and Shallow NLP
s In TREC-10, we participated in the web track (only ad-hoc task) and the QA track (only main task). In the QA track, our QA system (SiteQ) has general architecture with three proc...
Gary Geunbae Lee, Jungyun Seo, Seungwoo Lee, Hanmi...