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» Hardware Architecture of a Parallel Pattern Matching Engine
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DAC
2005
ACM
15 years 10 months ago
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Channel estimation and multiuser detection are enabling technologies for future generations of wireless applications. However, sophisticated algorithms are required for accurate c...
Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timoth...
BIBE
2008
IEEE
142views Bioinformatics» more  BIBE 2008»
15 years 4 months ago
Optimizing performance, cost, and sensitivity in pairwise sequence search on a cluster of PlayStations
— The Smith-Waterman algorithm is a dynamic programming method for determining optimal local alignments between nucleotide or protein sequences. However, it suffers from quadrati...
Ashwin M. Aji, Wu-chun Feng
EUROSYS
2007
ACM
14 years 11 months ago
Enabling scalability and performance in a large scale CMP environment
Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While exist...
Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghul...
IEEEPACT
2009
IEEE
15 years 4 months ago
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
Qingda Lu, Christophe Alias, Uday Bondhugula, Thom...
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HOTI
2002
IEEE
15 years 2 months ago
Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches
High-performance input-queued switches require highspeed scheduling algorithms while maintaining good performance. Various round-robin scheduling algorithms for Virtual Output Que...
Jing Liu, Chun Kit Hung, Mounir Hamdi, Chi-Ying Ts...