117 search results - page 16 / 24 » Hardware Compilation for FPGA-Based Configurable Computing M... |
108
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ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...
BIRTHDAY
1994
Springer
15 years 1 months ago
1994
Springer
Cook's construction from 1971 [4] shows that any two-way deterministic pushdown automaton (2DPDA) can be simulated in time O(n), where n is the length of its input string, and...
73
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IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
93
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MICRO
1996
IEEE
15 years 1 months ago
1996
IEEE
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and a...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...