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» Hardware Evaluation of the AES Finalists
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CHES
2003
Springer
146views Cryptology» more  CHES 2003»
15 years 1 months ago
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...
François-Xavier Standaert, Gaël Rouvro...
ISCAS
2008
IEEE
101views Hardware» more  ISCAS 2008»
15 years 4 months ago
High-performance ASIC implementations of the 128-bit block cipher CLEFIA
— In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/I...
Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Ak...
LCN
2006
IEEE
15 years 3 months ago
Practical Evaluation of the Performance Impact of Security Mechanisms in Sensor Networks
Security has become a major concern for many realworld applications for wireless sensor networks (WSN). In this domain, many security solutions have been proposed. Usually, all th...
Martin Passing, Falko Dressler
CHES
2007
Springer
154views Cryptology» more  CHES 2007»
15 years 3 months ago
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert ...
CHES
2011
Springer
254views Cryptology» more  CHES 2011»
13 years 9 months ago
Extractors against Side-Channel Attacks: Weak or Strong?
Randomness extractors are important tools in cryptography. Their goal is to compress a high-entropy source into a more uniform output. Beyond their theoretical interest, they have ...
Marcel Medwed, François-Xavier Standaert