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FPL
2007
Springer
115views Hardware» more  FPL 2007»
15 years 3 months ago
Hardware/Software Process Migration and RTL Simulation
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
Aric D. Blumer, Cameron D. Patterson
ARC
2009
Springer
175views Hardware» more  ARC 2009»
15 years 4 months ago
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve comput...
Brendan P. Glackin, Jim Harkin, T. Martin McGinnit...
FCCM
2006
IEEE
162views VLSI» more  FCCM 2006»
15 years 3 months ago
Power Visualization, Analysis, and Optimization Tools for FPGAs
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
Matthew French, Li Wang, Michael J. Wirthlin
ESM
2000
14 years 11 months ago
SEP: Simulation framework to evaluate digital hardware architectures
Know-how is the most useful mean for designing new processors before a complete hardware description. The integration rate is increasing very quickly and the timeto-market has to ...
Frédéric Mallet, Fernand Boér...
DSD
2007
IEEE
217views Hardware» more  DSD 2007»
15 years 4 months ago
Component-Based Hardware/Software Co-Simulation
Developing highly efficient and reliable embedded systems demands hardware/software (HW/SW) co-design and, therefore, co-simulation. In order to be highly configurable, embedded...
Ping Hang Cheung, Kecheng Hao, Fei Xie