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VIS
2005
IEEE
128views Visualization» more  VIS 2005»
15 years 11 months ago
Hardware-Accelerated Simulated Radiography
We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulatio...
Cláudio T. Silva, Daniel E. Laney, Nelson L...
ACSD
2003
IEEE
125views Hardware» more  ACSD 2003»
15 years 2 months ago
Modelling a Secure, Mobile, and Transactional System with CO-OPN
Modelling complex concurrent systems is often difficult and error-prone, in particular when new concepts coming from advanced practical applications are considered. These new appl...
Didier Buchs, Stanislav Chachkov, David Hurzeler
DATE
2003
IEEE
114views Hardware» more  DATE 2003»
15 years 2 months ago
Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering
This paper presents a new technique for automatically creating analog circuit models. The method extracts - from trained neural networks - piecewise linear models expressing the l...
Simona Doboli, Gaurav Gothoskar, Alex Doboli
ICCAD
2000
IEEE
169views Hardware» more  ICCAD 2000»
15 years 2 months ago
Transistor-Level Timing Analysis Using Embedded Simulation
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
Pawan Kulshreshtha, Robert Palermo, Mohammad Morta...
97
Voted
JUCS
2002
146views more  JUCS 2002»
14 years 9 months ago
A Framework for Semantics of UML Sequence Diagrams in PVS
: This paper presents a framework for representing formal semantics of a subset of the Unified Modeling Language (UML) notation in a higher-order logic, more specifically semantics...
Demissie B. Aredo