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JAIR
2006
137views more  JAIR 2006»
14 years 9 months ago
Learning Sentence-internal Temporal Relations
In this paper we propose a data intensive approach for inferring sentence-internal temporal relations. Temporal inference is relevant for practical NLP applications which either e...
Maria Lapata, Alex Lascarides
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
15 years 4 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 3 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
ICCAD
2006
IEEE
113views Hardware» more  ICCAD 2006»
15 years 6 months ago
A new statistical max operation for propagating skewness in statistical timing analysis
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...
Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylv...
MICRO
2002
IEEE
164views Hardware» more  MICRO 2002»
15 years 2 months ago
A quantitative framework for automated pre-execution thread selection
Pre-execution attacks cache misses for which conventional address-prediction driven prefetching is ineffective. In pre-execution, copies of cache miss computations are isolated fr...
Amir Roth, Gurindar S. Sohi