4074 search results - page 715 / 815 » Hardware Modelling and Simulation Using an Object-Oriented M... |
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
CODES
2008
IEEE
15 years 4 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...
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SIGMETRICS
2000
ACM
15 years 2 months ago
2000
ACM
— The conventional wisdom has been that IP is the natural protocol layer for implementing multicast related functionality. However, more than a decade after its initial proposal,...
HPCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...