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144
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ISQED
2003
IEEE
15 years 11 months ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
172
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ISQED
2003
IEEE
15 years 11 months ago
2003
IEEE
In this paper, we evaluate the dependencies between tools, data and environment in process design kits, and present a framework for systematically analyzing the quality of the des...
130
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
While the IEEE P1500 standards working group is on the verge of recommending a standard test interface for "non-mergeable" cores, a need was felt to adopt a standard met...
146
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in t...
160
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Intra-iteration data reuse occurs when multiple array references exhibit data reuse in a single loop iteration. An optimizing compiler can exploit this reuse by clustering (in the...