163 search results - page 21 / 33 » Hardware Performance Characterization of Block Cipher Struct... |
104
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DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
117
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ICIP
2006
IEEE
16 years 1 months ago
2006
IEEE
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
MICRO
1996
IEEE
15 years 3 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
ISLPED
1995
ACM
15 years 3 months ago
1995
ACM
We present a technique that automatically synthesizes nite state machines with gated clocks to reduce the power dissipation of the nal implementation. We describe a new transfor...
ASYNC
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...