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ICCD
2001
IEEE
112views Hardware» more  ICCD 2001»
15 years 6 months ago
Run-Time Execution of Reconfigurable Hardware in a Java Environment
We present tools that support the runtime execution of applications that mix software running on networks of workstations and reconfigurable hardware. We use JHDL to describe the ...
Laurie A. Smith King, Heather Quinn, Miriam Leeser...
88
Voted
DATE
2008
IEEE
134views Hardware» more  DATE 2008»
15 years 4 months ago
Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence
This paper presents a novel architecture for on-chip neural network training using particle swarm optimization (PSO). PSO is an evolutionary optimization algorithm with a growing ...
Amin Farmahini Farahani, Seid Mehdi Fakhraie, Saee...
NIPS
2004
14 years 11 months ago
Edge of Chaos Computation in Mixed-Mode VLSI - A Hard Liquid
Computation without stable states is a computing paradigm different from Turing's and has been demonstrated for various types of simulated neural networks. This publication t...
Felix Schürmann, Karlheinz Meier, Johannes Sc...
DAC
2002
ACM
15 years 10 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
ANNS
2010
14 years 7 months ago
A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System
In this contribution we will provide the reader with outcomes of the development of a novel software framework for an unique wafer-scale neuromordware system. The hardware system i...
Matthias Ehrlich, Karsten Wendt, Lukas Zühl, ...