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ICANN
2005
Springer
15 years 3 months ago
A Real-Time, FPGA Based, Biologically Plausible Neural Network Processor
Abstract. A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project,...
Martin J. Pearson, Ian Gilhespy, Kevin N. Gurney, ...
RSP
2006
IEEE
116views Control Systems» more  RSP 2006»
15 years 3 months ago
Performance Evaluation of an Adaptive FPGA for Network Applications
This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBla...
Christoforos Kachris, Stamatis Vassiliadis
ISCOPE
1998
Springer
15 years 1 months ago
Dynamic Reconfiguration and Virtual Machine Management in the Harness Metacomputing System
Metacomputing frameworks have received renewed attention of late, fueled both by advances in hardware and networking, and by novel concepts such as computational grids. However the...
Mauro Migliardi, Jack Dongarra, Al Geist, Vaidy S....
FCCM
2007
IEEE
168views VLSI» more  FCCM 2007»
14 years 9 months ago
Discrete-Time Cellular Neural Networks in FPGA
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
J. Javier Martínez-Álvarez, F. Javie...
FPL
2007
Springer
80views Hardware» more  FPL 2007»
15 years 3 months ago
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems
A temporal correlation based port combination algorithm that customizes the router design in Network-on-Chip (NoC) is proposed for reconfigurable systems in order to minimize req...
Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi,...